1. Technical Field
Example embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a semiconductor device including charge trapping layer patterns separated from each other, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A conventional non-volatile semiconductor memory device, which can be electrically programmed and erased, generally a unit cell having a floating gate type. However, the floating gate type unit cell may not properly meet requires electrical characteristics and storage capacity according as the non-volatile semiconductor memory device has minute dimensions. Accordingly, a silicon-oxide-nitride-oxide-silicon (SONOS) type unit cell has been employed in a recent non-volatile semiconductor memory device instead of the floating gate type unit cell.
FIG. 1 is a cross sectional view illustrating a SONOS type unit cell of a conventional non-volatile semiconductor memory device.
Referring to FIG. 1, the conventional SONOS type unit cell usually include a tunnel oxide layer, a silicon oxide nitride layer, a silicon oxide layer and a control gate sequentially formed on a silicon substrate. The silicon nitride layer serves as a charge trapping layer. Impurity regions BL1 and BL2 serving bit lines are located at portions of the silicon substrate adjacent to the tunnel oxide layer.
As for the conventional SONOS type unit cell on the non-volatile semiconductor memory device, however, an electrical disturbance may occur between adjacent impurity regions BL1 and BL2 when the SONOS type unit cell has extremely minute dimensions to improve storage capacity of the recent non-volatile semiconductor memory device. Particularly, charges may not be properly transferred between the impurity regions BL1 and BL2 in the programming and erasing operations of the non-volatile semiconductor memory device, thereby deteriorating electrical characteristics and reliability of the non-volatile semiconductor memory device. Further, the conventional SONOS type unit cell has a planar cell structure in which a plurality of layers are vertically stacked, so that the conventional SONOS type unit cell may not sufficiently ensure fine cell dimensions required in a highly integrated semiconductor memory device.